1. Field of the Invention
This invention relates to comparators, and more particularly to comparators for flash analog to digital converters utilized in data storage systems such as, for example, magnetic disk storage systems having read/write channel circuits.
2. Description of Related Art
In data storage systems data is stored on a storage media such as a CD-ROM, writable CD, DVD or other optical disk, magnetic tape, magnetic hard disk, etc. Typically, when data is read from the storage media, some form of data detection circuitry is utilized to process the signal generated from the storage media. In magnetic disk storage systems for computers, such as hard drives, digital data serves to modulate the current in a read/write head coil so that a sequence of corresponding magnetic flux transitions are written on a magnetic medium in concentric tracks. To read this recorded data, the read/write head passes over the magnetic medium and transduces the recorded magnetic transmissions into a signal of an analog nature that contains pulses that alternate in polarity. These pulses are then decoded by read/write channel circuitry to reproduce the digital data.
Decoding the pulses into a digital sequence can be performed by a simple peak detector in an analog read channel or, as in more recent designs, by using a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interferences (ISI) and, therefore, can recover pulses recorded at high densities. As a result, discrete time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete time sequence detection methods for use in a sampled amplitude read/write channel circuit including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, partial response maximum likelihood (PRML) sequence detection, decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF). When discrete methods are utilized for sampled amplitude read channel systems, an analog to digital converter (ADC) is typically utilized to convert the high frequency data which is contained on disk.
One type of ADC which may be utilized to convert high frequency disk data is a flash ADC. Such an ADC may contain multiple comparators for conversion of the analog data to digital data. The comparators typically utilize amplifier circuits of some form. In general, a comparator may be a circuit that has two analog inputs, one digital output and one clock input such as shown in FIG. 1. As shown in FIG. 1, the comparator circuit 10 compares an input voltage (V1) 12 to a second input voltage (V2) 14 at an instance defined by a transition of the clock signal 16. The comparator output 18 is a binary signal which will be HIGH if the input voltage V1 is larger than the input voltage V2 at the clock transition time instance, or LOW if V1 is smaller than V2. Within this behavioral definition, the input voltage V1 is said to be connected at the non-inverting input, while the input voltage V2 is said to be connected at the inverting input of the comparator.
A large number of such comparators, interconnected as depicted in FIG. 1A, can perform an analog to digital conversion function. FIG. 1A depicts a typical flash analog to digital converter. The converter input signal (Vin) 27 is simultaneously applied at the non-inverting inputs of an arbitrary number of identical comparators 10. The inverting inputs are connected separately to a set of N different reference voltage sources 22 as shown in FIG. 1A. The set of N reference voltage sources 22 may generate N equally spaced reference voltages (Vref) with the lowest voltage level being the least significant bit (LSB) size of the ADC. Since the outputs of the comparators are digital signals, the comparison operation performs an analog to digital conversion. The ADC digital output 25 may be the N-bit thermometer code digital representation of the input signal 27.
A typical implementation of the comparator 10 is shown in FIG. 1B. The ADC input (Vin) 27 may first be provided to a track/hold circuit 32. The track/hold circuit 32 is clocked by the ADC clock signal 16. The track/hold circuit may be conceptually viewed as a switch and capacitor as shown in FIG. 1B. The ADC clock signal 16 effectively defines the time instances at which the comparison between the input signal (Vin) 27 and the reference voltage (Vref) 22 takes place. The output voltage of the track/hold circuit will remain constant for the entire time the ADC clock stays HIGH and the comparison operation may entirely take place within this time. The comparator 10 may also contains a number of high gain amplifier stages 34. The gain amplifier stages 34 essentially amplify the difference between Vin and Vref voltages to a level that is compatible to the digital logic circuitry input requirements. It may also be customary to resynchronize the digital output of the comparator with the ADC clock 16 by means of a clocked digital latch 36. The comparator 10 of FIG. 1B has several disadvantages which relate to the use of the track/hold circuit 32. The accuracy of the comparison operation is highly dependent on the how constant the track/hold output is during sample time and any other errors introduced by the track/hold circuit. Further, the maximum comparison time needs to generally be shorter than the hold time since the hold time cannot be larger than half of the clock cycle due to the finite amount of time that the sample operation requires. This results in comparison speed constraints on the design of the subsequent stages of the comparator. In addition, because the track/hold circuit is located at the front-end of the comparator, the accuracy of the comparator as a whole is greatly affected by the track/hold circuit accuracy.
Another comparator circuit design may utilize the circuit of FIG. 1B without the track/hold circuit. With such an approach, the first gain stage may be implemented as a differential pair with resistive loads. Such a comparator, however, suffers from large accuracy problems since generally the output of the first gain stage may be overdriven to the power supply rail and the recovery from the overdrive will follow very different trajectories depending on the rate at which the input voltage swings.
FIG. 1C shows another flash ADC comparator where a track/hold circuit was implemented. In FIG. 1C the track/hold implementation utilized a storage capacitor C1 in conjunction with an auto-zero switch 50. A switch 40 is controlled by the SIG signal such that when SIG is high the switch 40 connects the input signal V.sub.in to the capacitor C1. When the SIG signal is low, the switch 40 connects the reference voltage source V.sub.ref to the capacitor C1. The auto-zero switch 50 closes a negative feed-back loop around the amplifier 60 when the AZ signal is high. This feedback loop holds both the input V.sub.a and the output V.sub.o1 of the amplifier 60 at a zero voltage during the auto-zero cycle. The output of the amplifier 60 is resampled by the switch 62 controlled by the signal SHO, in conjunction with the storage capacitor C2. The resampled voltage is applied at the input of the analog latch 70. The analog latch 70 can be reset by the switch 80 controlled by the LATCHB signal such that the switch is closed when LATCHB is high.
The operation of the comparator of FIG. 1C will be explained in more detail with additional reference to FIG. 1D. At the beginning of each comparison, the AZ signal is high and switch 50 is closed keeping the top plate of the capacitor C1 at zero volts. At the same time the SIG signal is high and the V.sub.in input signal is applied to the capacitor 2. This means that the voltage across the capacitor C1 (V.sub.cap) will track the input voltage (see the T.sub.track times of FIG. 1D). At the end of the track time T.sub.track, the AZ signal goes low, rapidly succeeded by the SIG signal going low. This will freeze the voltage V.sub.cap across the capacitor C2 (as indicated by points 90 on the V.sub.cap graph) for the entire period the auto-zero switch 50 is opened (i.e. AZ is low). When the SIG signal goes low, the reference voltage V.sub.ref is applied to the capacitor C1. Obviously, if the voltage V.sub.in stored on the capacitor C1 is equal to V.sub.ref, than the voltage V.sub.a at the input of the amplifier 60 will remain zero. Otherwise, the voltage V.sub.a will be the difference between the voltage V.sub.in (i.e. the sample of the input when the AZ signal went low) and the reference voltage V.sub.ref. The amplifier 60 will amplify this constant difference by integrating over a finite amount of time, T.sub.hold as shown by the amplifier output V.sub.o1. The integration end point when the hold time has elapsed is point 92 on the V.sub.o1 graph. The latching of the amplifier output needs to be done simultaneously with the acquisition of a new sample. This is the reason for the second track/hold circuit which will store the voltage of V.sub.o1 at points 92 and apply it to the input of the analog latch for the entire duration of the track time. The analog latch will quickly take a decision that is exclusively depending on the polarity of V.sub.o1 at the instance the SHO signal goes low (i.e. switch 62 closed).
The comparator of FIGS. 1C and 1D has a number of limitations. First, the comparator utilizes a track/hold action and therefore capacitor C1 needs to be able to be quickly charged to V.sub.in within a track cycle. To accomplish this a small capacitance such as approximately 25 fF may be utilized. However, such a small capacitor does not hold the voltage for long periods of time. Thus, the information of the capacitor C2 must be refreshed often, for example every ADC clock cycle. Because the comparator stores the sampled V.sub.in input and compares it against the reference voltage, the reference voltage generator design must be made to settle switching transients every conversion cycle. Further, a long reset time is needed (the AZ signal low) which is approximately equal to one-half the ADC cycle. Finally, the comparator operates in a two staged pipe-line mode which introduces latency into the system.